The invention generally relates to a synchronization detection architecture for serial data communication.
A repeater may be used to relay data between two serial buses. In this manner, a repeater 5 (see FIG. 1) may receive signals (from a serial bus 10) that indicate data and generate signals on another serial bus 20 to relay the data between the buses 10 and 20. In the course of its operation, the repeater 5 sorts out valid data from noise to ensure the integrity of the communications between the two serial buses 10 and 20.
More particularly, the repeater 5 may include a receiver 12 to receive data from the serial bus 10 and a transmitter 14 to communicate data to the serial bus 20. In this manner, the receiver 12 may include a data recovery circuit (DRC) 16 to recover data from the signals that are received from the serial bus 10. Besides recovering data from the serial bus 10, the data recovery circuit 16 typically queues, or buffers, the received data to accommodate the difference between the rate at which the data is received from the serial bus 10 and the rate at which the transmitter 14 communicates data to the serial bus 20.
The data typically is communicated over the serial bus 10, 20 in data packets, or frames. The beginning of a particular frame is marked by a predetermined bit pattern called a start, or synchronization, field, and the repeater 5 may monitor the incoming data to detect the synchronization field to identify a valid frame. In this manner, the repeater 5 does not enable the transmitter 14 to communicate a frame to the serial bus 20 until the repeater 5 has detected the synchronization field that is associated with that frame.
To detect the synchronization field, the receiver 12 may include a synchronization detection circuit 18 that receives recovered bits from the data recovery circuit 16. In this manner, the synchronization detection circuit 18 monitors the recovered bits (from the data recovery circuit 16) to detect the synchronization field, and once detected, the synchronization circuit 18 enables (via a signal line 24) the transmitter 14 to communicate the associated frame to the serial bus 20. This frame includes the recovered bits of data that form the synchronization field and the proceeding recovered bits of data that form the remainder of the frame. Therefore, all bits of data that are recovered by the data recovery circuit 16 typically passes through the synchronization circuit 18 and then through the transmitter 14 before being communicated to the serial bus 20.
Unfortunately, because all data passes through the synchronization circuit 18, a significant delay may be introduced by the synchronization detection circuit 18, and this delay is in addition to any delay that is introduced by the data recovery circuit 16. For a chain of the repeaters 5, the delays that are introduced by each repeater 5 accumulate and may have a significant impact to the overall system performance. Furthermore, bits may be lost during the repeating process, and as a result, a new synchronization field may have to be regenerated for the retransmission of some frames.
Thus, there is a continuing need for an arrangement that addresses one or more of the problems that are stated above.